Advanced program verify for page mode flash memory

ABSTRACT

Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.

CONTINUING APPLICATION DATA

The present application is a continuation-in-part of PCT Application No.US 94/10331, filed Sep. 13, 1994, published as WO96/21227 Jul. 11, 1996,now U.S. patent application Ser. No. 08/325,467, filed Oct. 26, 1994,entitled FLASH EPROM INTEGRATED ARCHITECTURE, invented by Yiu, et al.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to flash EEPROM memory technology, andmore particularly to an improved flash EEPROM memory architecture forautomatic program verify and for page programming.

2. Description of Related Art

Flash EEPROMs are a growing class of non-volatile storage integratedcircuits. The memory cells in a flash EEPROM are formed using so-calledfloating gate transistors in which the data is stored in a cell bycharging or discharging the floating gate. The floating gate is aconductive material, typically made of polysilicon, which is insulatedfrom the channel of the transistor by a thin layer of oxide, or otherinsulating material, and insulated from the control gate of thetransistor by a second layer of insulating material.

The floating gate may be charged through a Fowler-Nordheim tunnelingmechanism by establishing a large positive voltage between the gate andsource or drain. This causes electrons to be injected into the floatinggate through the thin insulator. Alternatively, an avalanche injectionmechanism, known as hot electron injection, may be used by applyingpotentials to induce high energy electrons in the channel of the cellwhich are injected across the insulator to the floating gate. When thefloating gate is charged, the threshold voltage for causing the memorycell to conduct is increased above the voltage applied to the word lineduring a read operation. Thus, when a charged cell is addressed during aread operation, the cell does not conduct. The non-conducting state ofthe cell can be interpreted as a binary 1 or 0 depending on the polarityof the sensing circuitry.

The floating gate is discharged to establish the opposite memory state.This function is typically carried out by an F-N tunneling mechanismbetween the floating gate and the source or the drain of the transistor,or between the floating gate and the substrate. For instance, thefloating gate may be discharged through the drain by establishing alarge positive voltage from the drain to the gate, while the source isleft at a floating potential.

The high voltages used to charge and discharge the floating gate placesignificant design restrictions on flash memory devices, particularly asthe cell dimensions and process specifications are reduced in size.

Furthermore, the act of charging and discharging the floating gate,particularly when using the F-N tunneling mechanism, is a relativelyslow process that can restrict the application of flash memory devicesin certain speed sensitive applications.

Another process which slows down flash memory devices is program verify.After applying a program sequence, successful programming must beverified, and if a failure is detected, then the programming is retried.Program retries are typically executed word by word or byte by byte.Thus, bits successfully programmed in a byte with one failed bit aresubjected to the program cycle repeatedly. This can result in overprogramming and failure of the cell. For one approach to this issue, seeU.S. patent application Ser. No. 5,163,021 by Mehrotra, et al., et seq.at col. 19, line 10 et seq. and FIGS. 14-17.

Therefore, it is desirable to provide a flash EEPROM cell architecture,and a method of programming the same which overcome speed penalties andover-programming failures of the prior art.

SUMMARY OF THE INVENTION

The present invention provides novel flash EEPROM cell and arraydesigns, and methods for programming the same which result in improvedspeed. The novel flash EEPROM array design is based on "page mode"programming, which operates by writing a row of data which constitutes apage, including, for example, as many as 1024 flash EEPROM cells inparallel. Thus, according to one aspect of the present invention, aflash EEPROM transistor array is provided. The memory array has aplurality of flash EEPROM cells for storing data. Supply circuits applyvoltages to the plurality of flash EEPROM cells to read and program theplurality of flash EEPROM cells in the memory array. A page bufferincluding a plurality of bit latches coupled to corresponding bit lines,provide for storage of a page of data to a row of flash EEPROM cellsalong a single wordline in the memory array. Control logic controls thesupply circuits in response to the memory data in the bit latches andaddress signals to program the data to the plurality of flash EEPROMcells in the row. Data verify circuits automatically verify successfulprogramming of the memory data to each cell in the row, and reset acorresponding bit latch upon successful verify. A page verified signalis generated when the row of cells pass verify as indicated by all bitlatches in the reset state; else the program operation is retried.

According to one aspect of the present invention, the memory arrayincludes at least M rows and N columns of flash EEPROM cells. The bitlatches provide the memory data for storage to the row of flash EEPROMcells so that the entire row of flash EEPROM cells is programmed in aprogramming sequence. After an entire row of flash EEPROM cells isprogrammed, the data in the programmed flash EEPROM cells are verified.The data verify circuits include verify logic which reads the memorydata from the flash EEPROM cell and resets the bit latch to provide acell data verify signal when the memory data from the flash EEPROM cellindicates a programmed state in the bit latch. Thus, the verify logicprovides for automatic program verify of the memory data in the flashEEPROM cell. The memory data from each flash EEPROM cell in the row offlash EEPROM cells is compared with the memory data in the correspondingbit latch and is automatically verified.

According to yet another aspect of the present invention, the dataverify circuits include output logic which provides the page verifysignal when all cell data verify signals are received for the flashEEPROM cells being verified. When the output logic does not provide thepage verify signal, retry logic reprograms flash EEPROM cells that failprogram verify. The retry logic further includes logic which countsreprogram retries and sets a reprogram limit on retries.

According to another aspect of the present invention, the program verifycircuitry includes logic which reads programmed input data from theflash EEPROM cells and compares the programmed input data with the dataof the bit latch to provide the program verified signal when allprogrammed flash EEPROM cells pass program verify. The logicautomatically provides the program verified signal when all programmedflash EEPROM cells pass program verify.

According to another characterization of the present invention, a methodof storing data in a memory array having M rows and N columns of FLASHEEPROM memory cells comprising the steps of loading a page buffer with arow of input data, selecting a row of memory cells for programming theinput data to the row of memory cells, programming the row of memorycells with the input data from the page buffer, reading the row ofmemory cells to verify programming of the input data to the row ofmemory cells, and setting a program verify flag when the input data inthe row of memory cells are verified. The memory array further comprisesthe step of reprogramming memory only cells which fail verify.

Other aspects and advantages of the present invention can be seen uponreview of the figures, the detailed description, and the claims whichfollow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic diagram of a flash EEPROM integrated circuitmodule according to the present invention.

FIG. 2 is a schematic diagram of a drain-source-drain configured,virtual ground, flash EEPROM array according to one embodiment of thepresent invention.

FIG. 3 is a schematic diagram of an alternative embodiment of thepresent invention with two columns of flash EEPROM cells sharing asingle metal bit line.

FIG. 4 is a schematic block diagram of a flash EEPROM array with pageprogram and automatic verify according to the present invention.

FIG. 5 is a simplified schematic showing program verify circuitryaccording to the present invention.

FIG. 6 is a schematic diagram showing a section of the page program andautomatic verify circuit for two memory cells in the flash EEPROM array.

FIG. 7 is a simplified circuit diagram of the page program and automaticverify circuit for a memory cell in the flash EEPROM array.

FIG. 8 is a timing diagram for control signals in the automatic verifycircuitry of FIGS. 6 and 7.

FIGS. 9A-9B illustrate a flow chart of a page program and automaticverify operation according to the present invention.

DETAILED DESCRIPTION

A detailed description of preferred embodiments of the present inventionis provided with respect to the figures, in which FIG. 1 provides aconceptual overview of a flash EEPROM integrated circuit moduleaccording to the present invention. Thus, the integrated circuit moduleof FIG. 1 includes a flash EEPROM memory array 100 as known in the art.

Coupled to the memory array 100 are word line and block select decoders104 for horizontal decoding in the memory array. Also coupled to thememory array 100 are the column decoder and virtual ground circuit 105for vertical decoding in the array.

Coupled to the column decoder and virtual ground circuit 105 are theprogram data in structures 103 and the sense amps 107, which providedata in and out circuitry coupled to the memory array.

The flash EEPROM integrated circuit typically is operated in a read onlymode, a program mode, and an erase mode. Thus, mode control circuitry106 is coupled to the array 100 to other blocks (108, 109, 105) on thechip.

Finally, according to one embodiment of the present invention, duringthe program and erase modes, a negative potential is applied to eitherthe gate or source and drain of the memory cells. Thus, a negativevoltage generator 108 and a positive voltage generator 109 are used forsupplying various reference voltages to the array. The negative voltagegenerator 108 and positive voltage generator 109 are driven by the powersupply voltage V_(CC) or alternatively by V_(CC) and a high programpotential V_(PP) as known in the art.

FIG. 2 illustrates one example design for two segments within a largerintegrated circuit. The segments are divided generally along dotted line50 and include segment 51A generally above the dotted line 50 andsegment 51B generally below the dotted line 50. A first pair 52 ofcolumns in segment 51A is laid out in a mirror image with a second pair53 of columns in segment 51B along a given global bit line pair (e.g.,bit lines 70, 71). As one proceeds up the bit line pair, the memorysegments are flipped so as to share virtual ground conductors 54A, 54B(buried diffusion) and metal-to-diffusion contacts 55, 56, 57, 58. Thevirtual ground conductors 54A, 54B extend horizontally across the arrayto a vertical virtual ground metal line 59 through metal-to-diffusioncontacts 60A, 60B. The segments repeat on opposite sides of the metalvirtual ground line 59 so that adjacent segments share a metal virtualground line 59. Thus, the segment layout of FIG. 2 requires two metalcontact pitches per column of two transistor cells for the global bitlines and one metal contact pitch per segment for the metal virtualground line 59.

Each of the pairs of columns (e.g., 52, 53) along a given bit line paircomprises a set of EEPROM cells. Thus, cells 75-1, 75-2, 75-N comprise afirst set of flash EEPROM cells in a first one of the pair 77 ofcolumns. Cells 76-1, 76-2, 76-N comprise a second set of flash EEPROMcells in the second column in the pair 77 of columns.

The first set of cells and the second set of cells share a common burieddiffusion source line 78. The cells 75-1, 75-2, 75-N are coupled toburied diffusion drain line 79. Cells 76-1, 76-2, 76-N are coupled toburied diffusion drain line 80. Selector circuitry comprising top selecttransistor 81 and top select transistor 82 couple the respective draindiffusion lines 79, 80 to metal global bit lines 83 and 84,respectively. Thus, the transistor 81 has a source coupled to the draindiffusion line 79 and a drain coupled to a metal contact 57. Transistor82 has a source coupled to the drain diffusion line 80 and a draincoupled to the metal contact 58. The gates of transistors 81 and 82 arecontrolled by the signal TBSEL_(A) to couple the respective columns offlash EEPROM cells to the global bit lines 83 and 84.

The source diffusion line 78 is coupled to the drain of selecttransistor 85. The source of select transistor 85 is coupled to avirtual ground diffusion line 54A. The gate of transistor 85A iscontrolled by the signal BBSEL_(A).

Furthermore, a sector of two or more segments as illustrated in FIG. 2may share word line signals because of the additional decoding providedby the top and bottom block select signals TBSEL_(A), TBSEL_(B),BBSEL_(A), and BBSEL_(B). In one embodiment, eight segments share wordline drivers, providing a sector eight segments deep.

As can be seen, the architecture according to the present inventionprovides a sectored flash EEPROM array. This is beneficial because thesource and drain of transistors in non-selected segments during a read,program or erase cycle may be isolated from the currents and voltages onthe bit lines and virtual ground lines. Thus, during a read operation,sensing is improved because leakage current from segments not selecteddoes not contribute to current on the bit lines. During the program anderase operations, the voltages of the virtual ground line, and the bitlines, are isolated from the unselected segments. This allows a sectorederase operation, either segment by segment or preferably sector bysector when the segments within a given sector share word line drivers.

It will be appreciated that the bottom block select transistors (e.g.,transistors 65A, 65B) may not be necessary in a given implementation asshown in FIG. 3 below. Also, these block select transistors may share abottom block select signal with an adjacent segment. Alternatively, thebottom block select transistors (e.g., 65A, 65B) may be replaced bysingle isolation transistors adjacent the virtual ground terminals 60A,60B.

FIG. 3 illustrates an alternative architecture of the flash EEPROM arrayaccording to the present invention, in which two columns of flash EEPROMcells share a single metal bit line. FIG. 3 shows four pairs of columnsof the array, where each pair of columns includes flash EEPROM cells ina drain-source-drain configuration.

Thus, the first pair 120 of columns includes a first drain diffusionline 121, a source diffusion line 122, and a second drain diffusion line123. Word lines WL0 through WL63 each overlay the floating gates of acell in a first one of the pairs of columns and a cell in the second oneof the pairs of columns. As shown in the figure, a first pair 120 ofcolumns includes one column including cell 124, cell 125, cell 126, andcell 127. Not shown are cells coupled to word lines WL2 through WL61.The second one of the pair 120 of columns includes cell 128, cell 129,cell 130, and cell 131. Along the same column of the array, a secondpair 135 of columns is shown. It has a similar architecture to the pair120 of columns except that it is laid out in a mirror image.

Thus, as can be seen, the transistor in the first one of the pair ofcolumns, such as the cell 125, includes a drain in drain diffusion line121, and a source in the source diffusion line 122. A floating gateoverlays the channel region between the first drain diffusion line 121and the source diffusion line 122. The word line WL1 overlays thefloating gate of the cell 125 to establish a flash EEPROM cell.

The column pair 120 and column pair 135 share an array virtual grounddiffusion 136 (ARVSS). Thus, the source diffusion line 122 of columnpair 120 is coupled to the ground diffusion 136. Similarly, the sourcediffusion line 137 of column pair 135 is coupled to the ground diffusion136.

As mentioned above, each pair 120 of columns of cells shares a singlemetal line. Thus, a block right select transistor 138 and a block leftselect transistor 139 are included. The transistor 139 includes a drainin the drain diffusion line 121, a source coupled to a metal contact140, and a gate coupled to the control signal BLTR1 on line 141.Similarly, the right select transistor 138 includes a source in thedrain diffusion line 123, a drain coupled to the metal contact 140, anda gate coupled to the control signal BLTR0 on line 142. Thus, the selectcircuitry, including transistors 138 and 139, provides for selectiveconnection of the first drain diffusion line 121 and a second draindiffusion line 123 to the metal line 143 (MTBL0) through metal contact140. As can be seen, column pair 135 includes left select transistor 144and right select transistor 145 which are similarly connected to a metalcontact 146. Contact 146 is coupled to the same metal line 143 as iscontact 140 which is coupled to column pair 120. The metal line can beshared by more than two columns of cells with additional selectcircuitry.

The architecture shown in FIGS. 2 and 3 is based upon adrain-source-drain unit forming two columns of cells which are isolatedfrom adjacent drain-source-drain units to prevent leakage current fromadjacent columns of cells. The architecture can be extended to units ofmore than two columns, with appropriate tolerances for leakage currentin the sensing circuitry, or other controls on current leakage fromunselected cells. Thus, for instance, fourth and fifth diffusion linescould be added within a given isolated region to create adrain-source-drain-source-drain structure which provides four columns ofcells.

Column pairs are laid out horizontally and vertically to provide anarray of flash EEPROM cells comprising M word lines and 2N columns. Thearray requires only N metal bit lines each of which is coupled to a pairof columns of flash EEPROM cells through select circuitry, as describedabove.

Although the figure only shows four column pairs 120, 135, 150, and 151,coupled to two metal bit lines 143 and 152 (MTBL0-MTBL1), the array maybe repeated horizontally and vertically as required to establish a largescale flash EEPROM memory array. Thus, column pairs 120 and 150 whichshare a word line are repeated horizontally to provide a segment of thearray. Segments are repeated vertically. A group of segments (e.g.,eight segments) having respective word lines coupled to a shared wordline driver may be considered a sector of the array.

The layout of the array is compact because of the virtual groundconfiguration, the reduced metal pitch requirement for the layout, andfurther by the ability to share word line drivers amongst a plurality ofrows in different segments. Thus, word line WL63' may share a word linedriver with word line WL63. In a preferred system, eight word linesshare a single word line driver. Thus, only the pitch of one word linedriver circuitry is needed for each set of eight rows of cells. Theadditional decoding provided by the left and right select transistors(139, 138 for segment 120) allows the shared word line configuration.The shared word line configuration has the disadvantage that during asector erase operation, eight rows of cells all receive the same wordline voltage, causing a word line disturbance in cells that are notdesired to be erased. If it is a problem for a given array, thisdisturbance problem can be eliminated by insuring that all sector eraseoperations decode for segments including all rows of cells coupled tothe shared word line drivers. For eight word lines sharing a singledriver, a minimum sector erase of eight segments may be desired.

FIG. 4 is a schematic block diagram of a flash EEPROM array meant toillustrate certain features of the present invention. Thus, the flashEEPROM memory module shown in FIG. 4 includes a main flash EEPROM array,including sectors 170-1, 170-2, 170-3, 170-N, each sector includingeight segments (e.g., SEG0-SEG7). A plurality of sets of shared wordline drivers 171-1, 171-2, 171-3, 171-N are used to drive the sharedword lines of the eight segments in the respective sectors. Asillustrated with respect to shared word line drivers 171-1, there are 64shared drivers for sector 170-1. Each of the 64 drivers supplies anoutput on line 172. Each of these outputs is used to drive eight wordlines in respective segments of the sector 170-1 as schematicallyillustrated in the figure by the division into eight sets of 64 lines.

Also coupled to the array are a plurality of block select drivers 173-1,173-2, 173-3, 173-N. The block select drivers each drive a left andright block select signal for each segment. Where the segments areimplemented as shown in FIG. 3, there is a BLTR1 and BLTR0 block selectsignal pair supplied for each set of 64 word lines.

In addition, there are N global bit lines in the flash EEPROM array. TheN bit lines are used to allow access to the 2N columns of flash EEPROMcells in the array for the data in circuitry and sense amps 191. Thecolumn select decoder 175 is coupled to the page program bit latches190, including at least one bit latch for each of the N bit lines. Also,the column select decoder 175 is coupled to the data in circuitry andsense amps 191. Data bus line 192 is 16 bits wide and provides inputdata to the data in circuitry and sense amps 191. Data bus line 192 alsoprovides 16 bits of output data. Together, these circuits provide datain and out circuitry for use with the flash EEPROM array.

The N bit lines 174 are coupled to a column select decoder 175. In apreferred system, N=1024 for a total of 1024 bit lines. The block selectdrivers 173-1 through 173-N are coupled to a block decoder 176. Theshared word line drivers 171-1 through 171-N are coupled to row decoder177. The column select decoder 175, block decoder 176, and row decoder177 receive address signals on the address in line 178.

Coupled to the column select decoder 175 is page program bitlatches/verify block 190. The page program bit latches/verify block 190includes N latches, one for each of the N bit lines. Thus, a page ofdata may be considered N bits wide, with each row of cells two pages,page 0 and page 1, wide. Pages in a given row are selected using theleft and right decoding described above. The page program bitlatches/verify block 190 includes verify circuitry for data stored inthe N bit latches and the N bits wide page of data programmed to aselected row of cells in the array. An example of this circuitry isdescribed below.

Selectable voltage sources 179 are used to supply the referencepotentials for the read, program, and erase modes for the flash EEPROMarray as conceptually illustrated in the figure, through the word linedrivers 171-1 to 171-N and through the bit lines.

The virtual ground lines in the array are coupled to the virtual grounddriver 181 providing potentials for the various modes to the virtualground terminals in the array. Also, p-well and n-well reference voltagesources 199 are coupled to the respective wells of the array.

Thus, as can be seen in FIG. 4, the 64 word line drivers, such as wordline drivers 171-1, are used with 512 (64×8) rows in the array. Theadditional decoding provided by the block select drivers (e.g., 173-1)allow for the shared word line layout.

The cells in the preferred embodiment are configured for a sector eraseoperation that causes charging of the floating gate (electrons enteringthe floating gate) such that upon sensing an erased cell, the cell isnon-conducting and the output of the sense amp is high. Also, thearchitecture is configured for a page program which involves discharginga floating gate (electrons leaving the floating gate) such that uponsensing, a programmed cell is conducting.

The operation voltages for the programming operation are positive 6volts to the drain of a cell to be programmed to a low (data=0)threshold condition, negative 8 volts to the gate, and 0 volts orfloating of the source terminal. The substrate or the p-well of the cellis grounded. This results in a Fowler-Nordheim tunneling mechanism fordischarging the floating gate.

The erase operation is executed by applying negative 8 volts to thedrain, positive 12 volts to the gate, and negative 8 volts to thesource. The p-well is biased at negative 8 volts. This results in aFowler-Nordheim tunneling mechanism to charge the floating gate. Theread potentials are 1.2 volts on the drain, 5 volts on the gate, and 0volts on the source.

This sets up the ability to do a sector erase using word line decodingto select cells to be erased. The erase disturbance condition forunselected cells within a segment results in -8 volts on the drain, 0volts on the gate, and -8 volts on the source. This is well within thetolerances of the cells to withstand these potentials without causingsignificant disturbance of the charge in the cell.

Similarly, the program disturbance conditions, for cells which share thesame bit line in the same segment are 6 volts on the drain, 0 volts onthe gate (or optionally 1 volt), and 0 volts or floating on the source.There is no gate to drain drive in this condition and it does notdisturb the cell significantly.

For cells which share the same word line but not the same bit line or anaddressed cell which is to remain in a high condition, the disturbancecondition is 0 volts on the drain, -8 volts on the gate, and 0 volts orfloating on the source. Again, this condition does not result insignificant deterioration of the charge in the unselected cells.

Referring to FIG. 4, the page program bit latch/verify block 190includes program verify circuitry which involves resetting on a bit bybit basis, the data in the page buffer that passes verify. Thus, astructure such as shown in conceptual form in FIG. 5 is included in theflash EEPROM. The sense amps 450 of the array are coupled to a comparecircuitry 451. The inputs to the compare circuitry are the page buffer/bit latches 452. Thus, a byte of data from the sense amps is comparedagainst a corresponding byte from the page buffer. A pass/fail signalfor the byte are fed back to a bit reset on the page buffer 452. Thus,bits which pass are reset in the page buffer. When all bits in the pagebuffer are reset, or a set number of retries of the program operationhas been accomplished, then the program operation is complete. Actually,no compare circuitry is needed according to one aspect of the invention.Rather, the sensed data can be used directly to reset passing bitlatches.

FIG. 6 is a schematic diagram of a section of the page program andautomatic verify circuitry for two bit lines MTBLO 143 and MTBL1 152.Metal line 143 (MTBL0) of FIG. 6 corresponds to metal line 143 (MTBL0)of FIG. 3. Metal line 152 (MTBL1) corresponds to metal line 152 (MTBL1)of FIG. 3. Array virtual ground 136 (ARVSS) of FIG. 6 corresponds to thearray virtual ground 136 (ARVSS) of FIG. 3. The signal PWI on line 501is coupled to the p-well of transistors 502, 504, 506, and 508. Eachpair of bitlines in the array has a similar structure coupled to it.

Referring to FIG. 6, the drain of transistor 502 and the drain oftransistor 504 are coupled to the metal line 143 (MTBL0). The drain oftransistor 506 and the drain of transistor 508 are coupled to the metalline 152 (MTBL1). The source of transistor of 504 and the source oftransistor of 506 are coupled to the array virtual ground 136 (ARVSS).Signal DMWLX on line 570 is coupled to gate of transistor 504 and gateof transistor 506. When signal DMWLX on line 570 is active, the arrayvirtual ground line 136 (ARVSS) is coupled to the metal line 143 (MTBL0)and the metal line 152 (MTBL1) via transistor 504 and transistor 506,respectively.

Data I/O line 574 is coupled to the source of transistor 502. Data I/Oline 576 is coupled to the source of transistor 508. Signal BLISOB online 572 is coupled to the gate transistor 502 and the gate oftransistor 508. When signal BLISOB is high, metal line 143 is coupled todata I/O line 574 via transistor 502, and metal line 152 is coupled todata I/O line 576 via transistor 508.

Data I/O line 574 is coupled to the drain of transistor 542. The sourceof transistor 542 is coupled to ground, and the gate of transistor 542is coupled to signal DMWL on line 588. The data I/O line 574 is pulleddown when the signal DMWL is high.

Data I/O line 574 is further coupled to the drain of column selecttransistor 544. The source of transistor 544 is coupled to node 551. Thegate of transistor 544 is coupled to signal Y0 on line 590.

A data in buffer 550 is coupled to the source of pass gate 552. Thedrain of pass gate 552 is coupled to node 551. Pass gate 552 iscontrolled by signal DINL on line 592.

Sense amp 554 is also coupled to node 551. Sense amp 554 is controlledby signal SAEB on line 594. The output of sense amp 554 is coupled tothe drain of pass gate 556. The source of pass gate 556 is coupled tolatch circuit 557. Pass gate 556 is controlled by signal SARD on line596.

The latch circuit includes inverters 558 and 560. The input of inverter558 is coupled to the source of pass gate 556. The output of inverter558 is coupled to the input of inverter of 560, and the output ofinverter 560 is coupled to the source of pass gate 556. The output oflatch circuit 557 is also coupled to a first input to NOR gate 562. Asecond input to NOR gate 562 is coupled to signal RESLATB on line 598.The output of NOR gate 562 is coupled to the gate of transistor 564. Thedrain of transistor 564 is coupled to node 551, and the source iscoupled to ground.

Data I/O line 576 which is coupled through transistor 508 to bit line152 is connected in a similar manner. Thus, line 576 is coupled to thedrain of transistor 548. The source of transistor 548 is coupled toground, and the gate is coupled to signal DMWL on line 588. The drain oftransistor 546 is also coupled to data I/O line 576. Signal Y0 iscoupled to the gate of transistor of 546. The source of transistor 546is coupled to node DATA1 591 which corresponds to node 551 for the otherside. For simplicity, a corresponding set of DIN buffer 550, sense amp554, latch circuit 557 and associated circuits coupled to node DATA1 591are not shown. In operation, circuits similar to DIN buffer 550, passgate 552, sense amp 554, pass gate 556, latch circuit 557, NOR gate 562,and transistor 564 are similarly configured and coupled to node DATA1591.

Each data I/O line 574, 576 has a bit latch/verify logic circuit coupledto it, comprised generally of the NAND gate 524 and inverter 526 fordata I/O line 574, and of NAND gate 534 and inverter 536 for data lineI/O 576. For data I/O line 574, the drain of pass gate 522 is coupled todata I/O line 574, and the source of pass gate 522 is coupled to a firstinput of NAND gate 524. A second input to NAND gate 524 is coupled tosignal BLATEN on line 582. The output of NAND gate 524 is coupled to theinput of inverter 526. The input power for NAND gate 524 and inverter526 is coupled to signal LATCHPWR on line 580. Signal LATCHB on line 578is coupled to the gate of pass gate 522. The output of inverter 526 iscoupled to the first input of NAND gate 524, the gate of transistor 510,and the gate of transistor 530. The drain of transistor 510 is coupledto signal ABLRES1 on line 577. The source of transistor 510 is coupledto ground. The drain of transistor 530 is coupled to signal DLPWR online 586. The source of transistor 530 is coupled to the drain oftransistor 528. The gate of transistor 528 is coupled to signal DLCTL online 584, and the source of transistor 528 is coupled to data I/O line574.

The data=1 state latched in latch circuitry 524 and 526 pulls downsignal ABLRES on line 577. The logic high level enables transistor 510which causes a logic low level on line 577. When transistor 510 isenabled, line 577 is coupled to ground which causes signal ABLRES to alogic low level. Transistors 514 and 516 comprise an inverter, which,together with transistors 510 and 512, provides a NOR logic function.Transistor 514 is a p-channel transistor with the source coupled to Vccand the drain coupled to the drain of n-channel transistor 516. Line 577is coupled to the drains of transistors 514 and 516. The source ofn-channel transistor 516 is coupled to ground, and the gates oftransistors 514 and 516 are coupled to signal PGPVB on line 599.Inverters 518 and 520 are coupled in series. Line 577 provides the inputto inverter 518. The output of inverter 518 provides the input ofinverter 520, and the output of inverter 520 provides signal ABLRES online 579. Thus, whenever latch circuitry 524 and 526 stores a logic highlevel, signal ABLRES is a logic low level. Transistor 514 provides apull-up to line 577 which can be driven to a logic low level by enablingeither transistor 510 or transistor 512.

The purpose of transistor 516 is that during default state PGFVB on line599 is "HIGH", and all the gates of transistors 510, 512 . . . are low,so that if there is no transistor 516, ABLRES1 on line 577 is floating.Transistor 516 is added to help line 577 to pull low in this case.During active mode, which is program-verify period during page programmode, PGPVB on line 599 is active "LOW", transistor 516 is off andtransistor 514 provides a pull-up to line 577.

A mirrored arrangement of circuits also controlled by signals LATCHB,LATCHPWR, BLATEN and DLCTL and are coupled to data I/O line 576. Thedrain of pass gate of 532 is coupled to data I/O line 576. The gate ofpass gate 532 is coupled to signal LATCHB on line 578. The source ofpass gate 532 is coupled to a first input to NAND gate 534. A secondinput to NAND gate 534 is coupled to signal BLATEN on line 582. Theoutput of NAND gate 534 is coupled to the input of inverter 536. SignalLATCHPWR on line 580 provides input power to NAND gate 534 and inverter536. The output of inverter of 536 is coupled to the first input of NANDgate 534, the gate of transistor of 512, and the gate of transistor 538.Signal DLPWR on line 586 is coupled to the drain of transistor 538. Thesource of transistor 538 is coupled to the drain of transistor 540. Thegate of transistor of 540 is coupled to signal DLCTL on line 584, andthe source of transistor 540 is coupled to data I/O line 576. The sourceof transistor 512 is coupled to ground and the drain of transistor 512is coupled to line 577.

FIG. 7 is a circuit diagram of a single bit latch for a bit line 602 inthe memory array, such as a line corresponding to the metal line 143(MTBL0) of FIG. 6. As in FIG. 6, the drain of transistor 502 is coupledto line 602. The source of transistor 502 is coupled to data I/O line574. The gate of transistor 502 is coupled to signal BLISOB on line 572.The width of transistor 502 is 20 microns, and the length of transistor502 is 1.2 microns. The drain of transistor 522 is coupled to data I/Oline 574, and the source of transistor 522 is coupled to a first inputof NAND gate 524. Signal LATCHB on line 578 is coupled to the gate oftransistor 522. The width of transistor 522 is 6 microns, and the lengthof transistor 522 is 1.2 microns.

Transistors 620, 621, 622, and 623 comprise NAND gate 524. Transistor624 and 625 comprise inverter 526. Signal LATCHPWR on line 578 providespower to NAND gate 524 and inverter 526. For example, the source ofp-channel transistor 620, the source of p-channel transistor 621, andthe source of p-channel transistor 624 are coupled to signal LATCHPWR online 578. The substrates of transistor 620, transistor 621, andtransistor 624 are also coupled to LATCHPWR on line 578. The gate oftransistor 620 is coupled to node 630 providing the first input of NANDgate 524. The gate of transistor 622 is further coupled to node 630. Thedrain of transistor 622 and the drain of transistor 621 are coupled tothe drain of transistor 620. The gate of transistor 621 and the gate oftransistor 623 are coupled to signal BLATEN on line 582. Signal BLATENon line 582 provides a second input to NAND gate 524. The drain oftransistor 623 is coupled to the source of transistor 622, and thesource of transistor 623 is coupled to ground.

The drain of transistor 621 provides the output of NAND gate 524 and iscoupled to the input of inverter 526. The gate of transistor 624 and thegate of transistor 625 provide the input to inverter 526. The source oftransistor 624 is coupled to signal LATCHPWR on line 578 to providepower to inverter 526. The drains of transistor 624 and transistor 625are coupled to node 630 and provide the output to inverter 526. Thesource of transistor 625 is coupled to ground. The substrate oftransistor 624 is coupled to signal LATCHPWR on line 578.

Transistors 621 and 624 have a width of 3 microns and a length of 1.4microns. Transistor 620 has a length of 1.6 microns and a width of 3microns. Transistor 622 and transistor 623 have a width of 3 microns anda length of 1.2 microns. Transistor 625 has a width of 3 microns and alength of 2 microns.

The output of latch circuitry 524 and 526 is coupled to the gate oftransistor 530 and the source of transistor 522. Signal DLPWR on line586 is coupled to the source of transistor 530. The drain of transistor530 is coupled to the source of transistor 528. The gate of transistor528 is coupled to signal DLCTL on line 584. The drain of transistor 528is coupled to data I/O line 574. Transistor 530 and transistor 528 havea width of 6 microns and a length of 1.2 microns.

The drain of transistor 510 provides output signal ABLRES1 on line 577.The source of transistor 510 is coupled to ground, and the gate oftransistor 510 is coupled to node 630. Thus, depending on the state ofthe bit latch, signal ABLRES1 is either shorted to ground or pulled upby transmitter 514. The width of transistor 510 is 3 microns and thelength is 0.8 microns.

The drain of transistor 544 is coupled to data I/O line 574, and thesource is coupled to data line 650. Signal YSEL on line 590 is coupledto the gate of transistor 544 on line 590. DIN buffer 550 is coupled todata line 650. Sense amp 554 is coupled to data line 650 and provides acontrol signal to the gate of transistor 564. The drain of transistor564 is coupled to data line 650, and the source of transistor 564 iscoupled to ground. Thus, depending on the output of sense amp 554,transistor 564 couples data line 650 to ground.

In operation, the page program and automatic verify circuit of the flashEEPROM array as shown in FIGS. 6 and 7 executes the page program andprogram verify in a series of stages. The stages can be generalized as a(1) data loading stage; (2) data program stage; (3) read the array datastage; (4) reset bit latch stage; and (5) retry stage. The operation ofthe page program and automatic verify of the flash EEPROM array isdescribed with reference to data I/O line 574. Page program andautomatic verify are similarly performed using data I/O line 576 that iscoupled to another memory cell. Furthermore, the page program andautomatic verify circuit includes similar circuitry for all data I/Olines needed to program a page of memory cells in the flash EEPROMarray.

In the data loading stage, signal LATCHPWR on line 580, signal LATCHB online 578, and signal BLATEN on line 582 are supplied with 5 volts toactivate data latch circuitry 524 and 526 for operation. Signal LATCHPWRon line 580 supplies voltage to NAND gate 524 and inverter 526 foroperation. Signal BLATEN on line 582 enables latch circuitry 524 and 526to receive inputs. Signal LATCHB on line 578 enables pass gate 522 tocouple data I/O line 574 with the first input of NAND gate 524. SignalBLISOB on line 572 is at a logic low level which disables transistor502. Disabling transistor 502 isolates data I/O line 574 from the metalline 143 (MTBL0). Signal DLCTL on line 584 is at a logic low level whichdisables pass gate 528. Signal DLPWR is at a logic high level having avoltage of Vcc that is approximately 5 volts. Signal DMWL on line 588 isat a logic low which prevents transistor 542 from coupling data I/O line574 to ground. Signal Y0 on line 590 is a logic high level which enablestransistor 544 to conduct. Signal Y0 is a decoded signal which enablesdata I/O line 574 to access a corresponding one of 16 DIN buffers (e.g.buffer 550) during the data loading stage. Signal DINL on line 592 is alogic high which enable pass gate 552. Input data from DIN buffers 550is transferred via pass gate 552 to data I/O line 574.

Once input data is transferred to data I/O line 574, the data from DINbuffer 550 is transferred to the first input of NAND gate 524. If datafrom DIN buffer 550 is a logic high level, the logic high level receivedat the first input of NAND gate 524 causes a logic low output. The logiclow output of NAND gate 524 provides the input to inverter 526 whichprovides a logic high output. NAND gate 524 and inverter 526 comprisethe bit latch circuitry 524 and 526 which latches the data received atthe first input of NAND gate 524. The logic high level at the output ofinverter 526 enables pass gate 530 and transfers signal DLPWR on line586 to pass gate 528. However, during the data loading stage, signalDLCTL on line 584 is a logic low which disables pass gate 528 fromconducting signal DLPWR to data I/O line 574.

In the other case, when data from DIN buffer 550 is a logic low level,the logic low level received at the first input of NAND gate 524 causesa logic high output. The logic high output of NAND gate 524 provides theinput to inverter 526 which provides a logic low output that is storedin latch circuitry 524 and 526. The logic low at the output of inverter526 disables pass gate 530 and the transfer of signal DLPWR on line 586via pass gate 528 to data I/O line 574. Thus, the bit latch circuit ofNAND gate 524 and inverter 526 stores either the logic high level or thelogic low level of the input data which corresponds to the datatransferred from DIN buffer 550.

The bit latches for the entire page of 1024 bits are loaded 16 bits at atime. Once the input data from DIN buffers 550 is loaded into bit latchcircuitry 524 and 526 after execution of the data loading stage for allbit lines, a verify sequence is executed followed by the data writestage. The pre-writing verify loop (according to the sequence describedbelow) prevents over programming cells into depletion such as if a userprograms the page with the same data twice. A data write occurs when alogic high is stored in the latch circuitry 524 and 526. When a logichigh level data=1 state is received from DIN buffer 550, the logic highlevel is programmed to a cell of the flash EEPROM array during the datawrite stage. If a logic low level (data=0) is received from DIN buffer550 and stored in latch circuitry 524 and 526, the data write stage doesnot program the memory cell of the flash EEPROM.

In the present example, a logic high level (data=1) is transferred fromDIN buffer 550 and stored in bit latch circuitry 524 and 526. During theexecution of the data write stage, signal LATCHB on line 578 isdisabled. Signal LATCHB on line 578 is set to a logic low to disableinputs to latch circuitry 524 and 526. Signal LATCHPWR is set to a highvoltage to provide power to latch circuitry 524 and 526. Signal BLATENon line 582 is set to a high voltage level to enable the output of latchcircuitry 524 and 526. Signal BLISOB on line 572 is set to a highvoltage level to enable transistor 502. Transistor 502 couples data I/Oline 574 to metal line 143. Signal DLCTL on line 584 is set to a highvoltage level to enable pass gate 528. Signal DLPWR on line 586 is setto a high voltage. Signal Y0 on line 590 is a logic low level to disabletransistor 544. Signal DINL is a logic low level which decouples inputdata from DIN buffer 550 from data I/O line 574. Signal SAEB is a logiclow level to disable sense amp 554.

Once the control signals are properly initialized to perform the dataprogram stage, signal DLPWR on line 586 is transferred to data I/O line574. Signal DLPWR provides programming power to program a memory cell inthe flash EEPROM array. Thus, if latch circuitry 524 and 526 is latchedwith a data=1 state, pass gate 530 is enabled to permit signal DLPWR topass through pass gate 528. Signal BLISOB on line 572 enables transistor502 and couples signal DLPWR to the metal line 143 (MTBL0).

Referring to FIG. 3, enabling signal BLTR1 on line 141 or BLTR0 on line142 couples a column of cells to the metal line 143 and provides theprogramming voltage from signal DLPWR to program a particular memorycell 125 or 129 on the word line which is changed to -8 volts. Forinstance, if BLTR1 on line 141 is selected and word line WL1 isselected, the programming voltage from signal DLPWR is directed tomemory cell 125.

After the data from latch circuitry 524 and 526 is programmed to thememory cell, the circuitry is ready to verify automatically that thedata was properly programmed in the data write stage. This involves afive step sequence (A through E; see FIG. 8 for timing diagram) fordeciding whether to reset the bit latch as follows:

Step A

READ the real data from the non-volatile bit through the associatedsense amp (all 16 sense amps are activated at the same time, i.e. 16bits are read at the same time). The sensing result is stored in latch557 of FIG. 6. For example, in FIG. 6, to verify a selected cell from aspecified wordline, BLISOB (572) must be high (ON), selected Y (544, 546and 14 more of such devices) is on, sense amp (SA) 554 is activated (and15 other SA), SARD (596) is high to allow the sensing result pass to thelatch (557) and LATCHB (578), DLCTL (584) are at low voltage (OFF) sothat during this READ step, the bit latch consisting of 524 and 526 willnot be disturbed. The selected cell threshold voltage is sensed by theSA (554) via data line 574 and then stored in latch 557, after a certainamount of time which is long enough for the SA (554) to do the sensing.If after programming, the cell's threshold voltage (VT) is low enough(to the point that the SA 554 can tell that the cell is at low VT state)then the output of the inverter (560, or input of 558) will reflect alow level, SARD (596) is off and then SA (544) is disabled. The lowlevel is stored in latch (557), no matter what read happens during thenext 4 steps in sequence until the new locations need to be read again.If after programming, the selected cell VT is still read high, then theoutput of inverter 560 is at high level, i.e. a logic high level islatched in latch 557. Note that RESLATB (598) is HIGH in this step sothat whether latch 557 latched high or low will not affect device (564)because device 564 is OFF anyway.

Step B

DISCHARGE DATA LINES (all including selected and deselected) The purposeof this step will be explained in STEP D). The way of discharging thedata line 574 is by activating DMWL (588) to high, LATCHB at low, DLCTLat low, with all sense amps disabled, 564 and 552 are off. Transistor588 discharges charge stored in data line 574. BLISOB (572) is at lowlevel (BLISO of FIG. 8 is high) to isolate the long metal-bit-line(MTBL0) from the data line (574) so that the discharge sequence can beachieved faster.

Step C

PRE-CHARGE DATA LINES (selectively, according to the associated bitlatch) The purpose of this step will be explained in step D.) Duringthis step, DMWL is at low level, BLISOB is still at low level (BLISO ofFIG. 8 is high), whether the selected 16 data lines of the same word andother de-selected data lines should be precharged to a high voltagelevel or not is decided by the data which is stored in the bit latch.For example, in FIG. 6, during this step LATCHB (578) is still off,DLCTL (584) is switched from low to high, and data line 574 isprecharged to a high level by connecting DLPWR (a V_(CC) level powersource for this instance) to the data line (574) via devices 530 and 528if the output of inverter 526 (which is the gate of 530) is latched atHIGH level. Otherwise DLPWR cannot precharge data line 574 to a highlevel and the data line 574 should be still at a low voltage level dueto step B)

Step D

RESET BIT LATCH OR NOT? During this step LATCHB (578) is switched fromlow level to a high level, and RESLATB (598) switches from high to lowin order to reset bit latch (which consists of inverter 524 and 526) byturning on 564, if the output of inverter 560 is (latched) low (fromstep A). Since the selected cell is at low VT already, the bit latchcontent shall be reset so that for the next programming, high voltagepulse sequence, the cell which is at low VT shall not be programmed tolow VT again. There is a chance that the bit latch had been reset from aprevious verify loop step D) or was at reset state even before the firstprogramming sequence. In these cases, the subsequent reset bit latchstep is of no effect to the bit latch for the former case; and for thelatter case whether the selected cell is at high VT or not will notaffect the bit latch because that if the cell is at high VT, there is noresetting the bit latch (564 is OFF, from Steps A and D) and bit latchwas at reset state. If the cell was at low VT, then resetting the bitlatch again makes no difference to the contents of the bit latch. Thereis no comparison circuit needed in this implementation.

Note that LATCHB is a global signal to all the bit latches in the FLASHEEPROM design and the high level at the gates of 522, 532 . . . resultsin all bit latches talking to the associated data lines which means thatthe node of the output of inverter 526 will encounter a charge sharingwith the associated data line (574, for example). The driving capabilityof inverter 526 is designed to be a weak device in order that a properdata can be set (to fight against inverter 526) into the bit latch. Sowhen LATCHB (528) is HIGH, weak inverter (526) suffers a charge sharingissues which results in the uncertainty of the integrity of the bitlatch.

The purpose of steps B) and C) is to put the proper voltage level at thedata lines before getting into step D), i.e. before LATCHB (578)switches from low to high to avoid any "charge sharing issues", eventhough the circuitry can be designed as mentioned above to ensure properoperation without them. During step B), all data lines are discharged tolow level and then at step C) only those data lines whose associated bitlatches "stored" high level will be precharged to a high level. Thussteps B) and C) are optional steps inserted here for safety in thedesign.

Step E

DISCHARGE ALL DATA LINES AGAIN. At this moment, the program-verifyactivity is pretty much done, before moving into the next word forprogramming-verifying (or more precisely, to change the new word andrepeat from step A) to step D)), the logic control will remove residuecharges from all the data lines and switch to new word. For example,during this step, LATCHB (578) is at LOW level, RESLATB (598) is at HIGHlevel, DMWL (598) is at HIGH level and BLISOB (572) is at HIGH level(BLISO of FIG. 8 is low).

Thus, the page program and automatic verify circuit of FIG. 5 providesthe unique feature of automatically verifying a memory cell that isprogrammed. Latch circuitry 524 and 526 stores the input data receivedfrom DIN buffer 550. The stored data in latch circuitry 524 and 526controls ABLRES1 which is set to a logic low level if there is one ormore than one of the cells which need to be programmed. Signal ABLRES1remains a logic low level until the memory cell is verified during theprogram verify sequence which resets latch circuitry 524 and 526 to alogic low level and resets signal ABLRES1 to a logic high levelindicating a properly programmed memory cell. The program verifysequence is automatic.

Signal PGPVB on line 599 is a logic low level to supply a charge to line577 during automatic verify sequence. When latch circuitry 526 and 524is reset, transistor 510 is disabled and the charge on line 577 is nolonger discharged to ground. Signal ABLRES1 on line 577 becomes a logichigh level. The logic high level provides an input to inverter 518 whichproduces an output that provides an input to inverter 520 which providesthe logic high level output of signal ABLRES on line 579. The logic highlevel of signal ABLRES on line 579 provides a page programmed verifysignal signifying the page of memory cells has passed program verify.

Each memory cell within a page of memory cells in the array is able toactivate a transistor 510 to cause signal ABLRES1 on line 577 to a lowlevel. Thus, any memory cell that does not pass program verify within apage of memory cells in the array can cause the output ABLRES to be alogic low level. The logic low level of ABLRES on line 579 signals thatat least one memory cell within the page of memory cells in the array isnot properly programmed and verified. Thus, any memory cell not properlyverified can cause signal ABLRES on line 579 to be a logic low level.When all memory cells are properly programmed and verified, signalABLRES on line 579 is a logic high level.

In operation, unsuccessfully programmed memory cells are reprogrammedand reverified until signal ABLRES becomes a logic high level. Thenumber of retries are limited to prevent looping of the programmingsequence if a page repeatedly fails program verification.

FIGS. 9A-9B provide a flow chart illustrating the program flow for theflash EEPROM circuit of FIG. 6. The process begins by erasing the sector(e.g., sector 170-1) into which data is to be programmed (block 700).After erasing the sector, an erase verify operation is executed (block701). Next, the page number, either 0 or 1, and the segment number, 1-8,is set by the host processor in response to the input address (block702).

After setting the page number and segment number, the page buffer isloaded with the data for the page (block 703). This page buffer may beloaded with an entire N bits of data, or a single byte of data, as suitsa particular program operation. Next, a verify operation is executed, incase the user does not pre-erase or tries to reprogram the same data, todetermine which cells need programming (block 704). After loading thepage buffer, the program potentials are applied to the segment beingprogrammed (block 705). After the program page operation, a verifyoperation is executed in which the page is verified. In the verifyoperation, the programmed page is read and each corresponding read bitof data is stored in a sense amp data latch (block 715).

Referring to FIG. 9B, the page bits which pass verify are reset (block722). Next, the algorithm determines whether all page bits are turnedoff in the page buffer (block 723). If they are not all off, then thealgorithm determines whether a maximum number of retries has been made(block 710), and if not, loops to block 705 to program the page again,such that the failed bits are reprogrammed. The bits which pass are notreprogrammed because the corresponding bits in the page buffer werereset to 0 during the verify operation. If the maximum number of retrieshas been made at block 710, then the algorithm hangs up, signaling anunsuccessful operation.

If at block 723, all page bits were off, then the algorithm determineswhether the sector has been finished, that is, whether both pages of thesector are to be written and both are completed (block 725). This is aCPU determined parameter. If the sector is not finished, then thealgorithm loops to block 702 and updates the appropriate one of the pagenumber or segment number. If the sector has been finished at block 725,then the algorithm is done (block 730).

Accordingly, a new flash EEPROM cell and array architecture have beenprovided. The architecture provides for a very dense core array obtainedby unique cell layouts, where two adjacent local drain bit lines shareone common source bit line. Also, the layout has been optimized to allowuse of a single metal line for every two columns of cells in the array.Further, the layout is further reduced by shared word lines, so that theword line driver pitch does not impact the size of the main array.Sector erase is feasible using segmentable architecture of the presentinvention. Also, the page program and automatic verify circuitryprovides efficient and accurate programming of the memory cells. Thus, ahigh performance, reliable flash memory array can be achieved usingthese technologies.

An n-channel embodiment of the flash EEPROM array has been disclosed.Those skilled in the art will recognize that p-channel equivalentcircuits can be implemented using techniques known in the art.

Furthermore, the architecture has been designed with respect to flashEEPROM cells. Many aspects of the architecture may be adapted to avariety of memory circuit arrays.

The foregoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope ofthe invention be defined by the following claims and their equivalents.

What is claimed is:
 1. An apparatus for storing data, comprising:amemory array having a plurality of floating gate cells; supply circuits,coupled to the memory array, which apply voltages to the plurality offloating gate cells to read and program the plurality of floating gatecells in the memory array; a plurality of bit latches, coupled to thememory array, which provide a buffer for storage of data to a setincluding at least a portion of a row of floating gate cells in thememory array; control logic, coupled to the supply circuits and the bitlatches, which controls the supply circuits to program the data in theplurality of bit latches to the set of floating gate cells; andautomatic data verify circuits, coupled to the memory array and theplurality of bit latches, which verify successful programming of thedata to the set of floating gate cells in the memory array and provide adata verified signal when the row of plurality of floating gate cellspass data verify, the automatic data verify circuits including verifylogic, coupled to the bit latches and floating gate cells in the memoryarray, which reads the memory data from the floating gate cells andresets the corresponding bit latches when the read data indicates aprogrammed state.
 2. The apparatus of claim 1, wherein:each row ofplurality of floating gate cells includes a first page and second page;and the set includes a page of floating gate cells.
 3. The apparatus ofclaim 1, wherein:the memory array includes at least M word lines and Nbit lines coupled to the plurality of floating gate cells; and theplurality of bit latches includes one bit latch for each of the N bitlines; and N is greater than
 32. 4. The apparatus of claim 1, whereinthe data verify circuits include output logic, coupled to the verifylogic of each floating gate cell being verified, which provides the dataverified signal when all bit latches store a particular binary value. 5.The apparatus of claim 4, further comprising retry logic, coupled to thedata verify logic and the control logic, which reprograms floating gatecells having corresponding bit latches not storing the particular value.6. The apparatus of claim 5, wherein the retry logic includes logicwhich counts reprogram retries and sets a reprogram limit on retries. 7.A floating gate memory circuit module on a semiconductor substrate,comprising:a memory array including at least M rows and N columns offloating gate cells; M word lines, each coupled to the floating gatecells in one of the M rows of floating gate cells; a plurality of bitlines, each coupled to the floating gate cells in at least one of the Ncolumns of floating gate cells; a page buffer, including a plurality ofbit latches coupled to corresponding ones of the plurality of bit lines,which supplies input data to the N columns of floating gate cells; writecontrol circuitry, coupled to the page buffer and the M word lines,which supplies programming voltages to a selected word line forprogramming input data to a row of floating gate cells accessed by theselected word line in response to the input data stored in the pagebuffer; and program verify circuitry, coupled to the page buffer, whichverifies that floating gate cells are programmed with the input data incorresponding bit latches in the page buffer, and including logiccoupled to the page buffer, and to the bit lines, that resets bitlatches to a first binary value when stored data in a floating gate cellon a corresponding bit line matches a second binary value.
 8. Thefloating gate memory circuit of claim 7, wherein:a row of N columns offloating gate cells include a first page and a second page; and the pagebuffer supplies input data to a page of floating gate cells.
 9. Thefloating gate memory circuit of claim 7, wherein the program verifycircuitry includes logic responsive to stored data from the floatinggate cells and to data in the page buffer to provide the programverified signal when all programmed floating gate cells pass programverify.
 10. The floating gate memory circuit of claim 7, wherein theprogram verify circuitry generates a program verified signal when allbit latches store the first binary value.
 11. The floating gate memorycircuit of claim 10, wherein the write control circuitry applies a wordline program potential to a word line coupled to a selected set offloating gate cells, and a bit line program potential to bit linescoupled to bit latches storing the second binary value.
 12. A method ofstoring data in a memory array on an integrated circuit having M rowsand N columns of floating gate memory cells comprising the stepsof:loading a page buffer on the integrated circuit with a row of inputdata; selecting a row of memory cells for programming the input data tothe row of memory cells; programming the row of memory cells with theinput data from the page buffer; reading the row of memory cells toverify programming of the input data to the row of memory cells; andresetting the input data in the page buffer of successfully verifiedmemory cells in the row of memory cells and in response to dataremaining in the page buffer, retrying the steps of programming,reading, and resetting.
 13. The method of claim 12 further comprises thestep of selecting a subset of the N columns in the row of memory cellsfor programming the input data.
 14. The method of claim 12, wherein thestep of resetting the input data includes the step changing the inputdata stored in the page buffer from a program state to a do not programstate.
 15. The method of claim 12, wherein the step of programming therow memory cells includes the step of changing charge states stored inthe floating gate memory cells when a data program state is stored inthe page buffer.
 16. The method of claim 12 wherein the step of loadinga page buffer with a row of input data includes loading 16 bits of inputdata at a time to the page buffer.
 17. The method of claim 12 whereinthe step of programming the row memory cells with the input data fromthe page buffer includes programming one of 128, 256, 512 or 1024 bitsof input data to the row memory cells.
 18. A floating gate memorydevice, comprising:a memory array including at least M rows and Ncolumns of floating gate cells; M word lines, each coupled to thefloating gate cells in one of the M rows of floating gate cells; N bitlines, each coupled to the floating gate cells in one of the N columnsof floating gate cells; N bit latches, each coupled to one of the N bitlines, which receives input data having a program state and a do notprogram state for the N columns of floating gate cells; programcircuitry, coupled to the N bit latches, the N bit lines and the M wordlines, which applies programming voltages to a selected word line, andto bit lines coupled to bit latches storing a program state to programfloating gate cells coupled to the N bit lines in parallel in responseto data in the bit latches; and verify circuitry, coupled to the programcircuitry, which senses the N columns of floating gate cells to resetthe bit latches from the program state to the do not program state inresponse to properly programmed floating gate cells, and wherein theprogram circuitry retries programming the floating gate cells coupledcorresponding to bit latches that remain in the program state.
 19. Thefloating gate memory device of claim 18 wherein the verify circuitryprovides an all cell verified signal when all page bit buffers arereset.
 20. The floating gate memory device of claim 18 wherein theverify circuitry includes:latches which store cell data from floatinggate cells sensed during verify; and logic which resets the bit latcheswhen corresponding cell data of the latches indicates a programmed statewhich verifies proper programming of the floating gate cell.
 21. Anapparatus for storing data, comprising:a memory array having a pluralityof floating gate cells; supply circuits, coupled to the memory array,which apply voltages to the plurality of floating gate cells to read andprogram the plurality of floating gate cells in the memory array; aplurality of bit latches, coupled to the memory array, which provide abuffer for storage of data to a set including at least a portion of arow of floating gate cells in the memory array; control logic, coupledto the supply circuits and the bit latches, which controls the supplycircuits to program the data in the plurality of bit latches to the setof floating gate cells; and automatic data verify circuits, coupled tothe memory array and the plurality of bit latches, which verifysuccessful programming of the data to the set of floating gate cells inthe memory array, including verify logic, coupled to the bit latches andfloating gate cells in the memory array, which reads the memory datafrom the floating gate cells and resets the corresponding bit latcheswhen the read data indicates a programmed state.
 22. The apparatus ofclaim 21, wherein:each row of plurality of floating gate cells includesa first page and second page; and the set includes a page of floatinggate cells.
 23. The apparatus of claim 21, wherein:the memory arrayincludes at least M word lines and N bit lines coupled to the pluralityof floating gate cells; and the plurality of bit latches includes onebit latch for each of the N bit lines; and N is greater than
 32. 24. Theapparatus of claim 21, wherein the data verify circuits include outputlogic, coupled to the verify logic of each floating gate cell beingverified, which provides a data verified signal when all bit latchesstore a particular binary value.
 25. The apparatus of claim 21, furthercomprising retry logic, coupled to the data verify logic and the controllogic, which reprograms floating gate cells having corresponding bitlatches not storing the particular value.
 26. The apparatus of claim 25,wherein the retry logic includes logic which counts reprogram retriesand sets a reprogram limit on retries.